OpenAI and Synopsys, the largest supplier of chip design software, are building a model that does not just advise engineers but runs their tools. The companies said on 30 September that GPT-Synopsys will combine OpenAI's frontier models with Synopsys's electronic design automation software, and will operate that software as an expert user would: reading tool outputs, adjusting settings and iterating towards a design that meets its targets.
The model is aimed at the hardest parts of chip design, including the trade-offs between power, performance and area that consume much of a project's schedule, along with verification and timing closure. Engineers would set objectives and let the system work towards them, rather than driving each tool themselves.
Under a multi-year agreement, OpenAI licenses Synopsys's tools, the model runs on OpenAI-hosted infrastructure, and the two companies share revenue and sell jointly. Neither disclosed the split. Early engagements are under way with semiconductor customers that have not been named, and Synopsys shares rose nearly 5% on the announcement.
"By helping them build better chips, we can build better AI," said Greg Brockman, OpenAI's president and co-founder. Synopsys chief executive Sassine Ghazi said the partnership brings "frontier intelligence to chip design."
Why Design Software Is The Place To Put An Agent
Chip design is an unusually good fit for an agent because the work is slow, iterative and measurable. Verification alone accounts for roughly 65% of design time, running eight to 15 months on a complex chip, according to a market analysis by SemiAnalysis, while implementation takes about 30%.
Each step produces numerical results that tell the tool whether it did better or worse, which gives an AI system a clear signal to optimise against. That is rarer than it sounds in enterprise software, where most tasks lack an objective score.
The commercial logic is equally clear. Electronic design automation and the associated intellectual property made up an $18 billion market in 2025, heading towards $28 billion to $31 billion by 2030, and Synopsys, Cadence and Siemens hold more than 85% of it between them. Synopsys alone commands roughly 84% of logic synthesis and over 90% of signoff tools.
Lock-In Cuts Both Ways
That dominance is what makes the deal valuable to OpenAI. Chip design runs as a sequence in which each stage depends on the last, so changing one tool forces a team to redo everything downstream, and foundries including TSMC and Samsung specify which tools customers must use for tape-out. A model trained to operate inside that workflow inherits its stickiness.
For Synopsys, the risk runs the other way. If customers come to rely on an AI agent to drive the tools, the agent becomes the interface, and the company providing it gains influence over a relationship Synopsys has owned for decades.
OpenAI Has Its Own Reasons
Brockman's line about better chips making better AI is not a platitude. OpenAI agreed with Broadcom in late 2025 to co-develop custom AI accelerators and deploy 10 gigawatts of them, which makes OpenAI a chip designer as well as a model provider.
A model that can drive design tools serves that programme directly, shortening the path from an architecture idea to working silicon for the company's own accelerators. Every large AI company is now designing its own chips, and the pace shows in results such as the edge AI benchmarks we examined from Nvidia's latest hardware. The arrangement also gives OpenAI deep exposure to how advanced chips are actually built, knowledge that is hard to acquire any other way.
Cadence Got There First With Nvidia
Synopsys is responding to a rival that moved earlier. Cadence, the second largest EDA company, announced an autonomous design agent with Nvidia in June, claiming a 40-fold improvement in verification cycles and verification loops completed in under a day. The agent handles specification, RTL generation, verification planning, formal analysis, simulation and debugging inside an Nvidia sandbox. Cadence also works with Google on a chip design agent running on Google Cloud.
Each of the three leading EDA vendors has now paired with an AI company: Cadence with Nvidia and Google, Synopsys with OpenAI. The pattern says something about both sides, since the AI companies need chips and the EDA vendors need frontier models they cannot build themselves.
The Claims Need Testing
The productivity figures in this field deserve caution. A 40-fold improvement in verification cycles describes a benchmark rather than a finished chip, and no vendor has yet published results from a design taken all the way to tape-out by an agent working mostly on its own.
Synopsys has not claimed a specific speed-up for GPT-Synopsys, and has not said when it will be generally available. Early engagements with unnamed customers is an honest description of where this sits.
What Chip Teams Should Ask
For semiconductor companies, and for the growing number of systems companies designing their own silicon, the questions are practical. Data protection comes first: Synopsys says customer design data is not used to train the model, is encrypted and has configurable retention, which matters when a design file represents years of work and a company's core intellectual property.
Teams will also want to know how the model's decisions can be inspected and reproduced, since a chip that fails in silicon costs millions and months, and an engineer has to be able to explain why a tool made a particular trade-off. Pricing is the other unknown, because AI features in EDA have already pushed up renewal costs, with Synopsys reporting roughly 20% uplift when customers adopt them.
The wider effect may be on who can design chips at all. Hyperscalers and carmakers building custom silicon face a shortage of experienced designers, and tools that let smaller teams reach a working chip would widen the field, in the same way that cheaper design routes opened up board-level work for smaller teams.
The Tools Are Becoming The Operators
GPT-Synopsys marks a change in what AI does in engineering software. Rather than suggesting code or answering questions, the model is meant to sit in the operator's chair and run the tools, with the engineer setting goals and judging results.
Chip design is where that idea gets its first serious test, because the work is measurable, the stakes are high and the industry has an acute shortage of senior engineers. If an agent can carry a real design through verification and timing closure, the same pattern will arrive in other engineering disciplines that run on specialist software. If it cannot, the EDA vendors will have sold their customers a very expensive assistant.
